Masters Thesis

Secure ASIC design flow for reverse engineering prevention

Due to the rise of fabrication-less Integrated Circuit (IC) design companies that outsource IC manufacturing to third parties, hardware obfuscation is crucial in protecting ICs from reverse engineering. A Look-Up Table (LUT) built using Non-Volatile (NV) latches will be used to replace logic gates to obfuscate designs. Once a LUT is programmed with the correct configuration bits, it enables the LUT to function exactly like a target logic gate and is difficult to reverse engineer since the LUTs are empty memory cells during manufacturing. The NV latches used in the construction jf die LUTs is based on eFuse technology that is provided as hard macros from manufactures. To utilize these LUTs in ASIC designs, the normal ASIC flow will be modified to accommodate multiple hard macros during synthesis and automated process of placement, power routing, and net routing during physical design. This will be beneficial to IC designers as they can easily obfuscate their designs u ng LUTs with minimal overheard during the design process.

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