ASIC design flow using hybrid custom CMOS and look-up-table macro cells

Hardware security is becoming a significant threat to the IC design Industry, as many successful IC design manufacturers have decided to go fabless, due to expensive lithography. This paradigm shift has created a serious security threat because the in-house fabrication process, once monitored very closely, is now being outsourced to potentially untrusted facilities. A recent survey on the semiconductor industry by Semiconductor Equipment and Materials International (SEMI) reports that 90% of companies have experienced IP infringement. SRAM Based Look-Up-Table (LUT) soft Macro cell is a programmable logic used for mapping the logic gates in the design. In traditional LUT based methods such as FPGA based implementations, the entire logic circuits are mapped to LUTs, which offers high leakage power, high performance and area overheads. In order to combine the benefits of traditional standard cell and LUT based designs, a hybrid custom CMOS and LUT mapped design will be implemented, where some parts of the design is left as custom CMOS gates (i.e ASIC standard cells) and remaining mapped to SRAM based LUT Macro. In this research, we study the application of SRAM based LUT Macro to provide reconfigurability of a design and also automate the process of logic gate replacement with LUT. This approach is expected to hide the identity of the hardware from hackers who may attempt to reverse engineer a product to get access to intellectual property of design.