Non-volatile magnetic date retention flip-flop with separated precharge feedback sensing

Spin Transfer Torque RAM (STT-RAM) promises low power, great miniaturization prospective and easy integration with CMOS process. It has become a strong non-volatile memory candidate for both embedded and standalone applications. However, the increase in process variation and decrease in the supply voltage results in the degradation of the reliability. This research targets efficient design solutions to improve the reliability of the STT-based latches. The research investigates different sources of variability and aging in CMOS and Magnetic Tunnel Junction (MTJ) devices used in the STTRAM process. Different STT-Latch design styles are also investigated and their robustness against process variations are analyzed.