Design of 6-bit 2.5 b/stage pipelined analog-to-digital converter with redundancy algorithm

Neuromorphic computing system that emulates the biological nervous system is widely used in applications like pattern recognition, machine learning, and artificial intelligence. The mcmristor crossbar array based neural network has the potential to realize small-size and low-power neuromorphic computing. An efficient and high speed ADC is critically needed to read the output of the memristor crossbar array and transform it to the digital domain. In this thesis, a pipelined ADC is designed with 6-bit resolution, 20 MS/s sampling rate, and IV input range (0.1 V to 1.1 V), while maintaining minimal power consumption. The pipelined ADC uses a 2.5 b/stage redundancy with a sample-and-hold (SHA)-less architecture to minimize die area and data latency. Also, the redundancy algorithm is implemented to selfcorrect any comparator offset. The proposed ADC architecture is implemented using standard IBM 130 nm CMOS technology.